Method of fabricating semiconductor device with shallow trench isolation

ABSTRACT

In fabrication of a semiconductor device, a first insulating film, electrode film and silicon nitride film sequentially stacked on a semiconductor substrate are etched with the substrate so that a trench is formed. The electrode film is then exposed. A second insulating film buried in the trench is isotropically etched so that an upper side wall of the electrode film is exposed, so that a side end of an upper surface of the insulating film is located between the upper surfaces of the substrate and electrode film and so that a middle upper portion of an upper surface of the second insulating film is higher than the side end and lower than the upper surface of the first electrode film, A third insulating film is formed on the upper surface of the first electrode film so as to entirely cover the upper surface of the second insulating film.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 11/060,542filed on Feb. 18, 2005, all of which claim priority to Japanese PatentApplication No. 2004-043363 filed on Feb. 19, 2004. The contents of eachof these documents are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a semiconductordevice in which trenches are formed in a semiconductor substrate and aninsulator is buried in the trenches so that an element isolation regionis formed.

2. Description of the Related Art

The semiconductor device of the above-described type includesnon-volatile memories such as flash memories. In the non-volatilememories, an etching process requires high precision in a step offorming an element isolation region in a memory cell forming area.However, a conventional fabricating step involves factors which cannotimprove the precision in the following points. FIGS. 6A to 6E illustratetypical sectional structures of a semiconductor device according to aconventional fabricating method. In FIG. 6A, firstly, a silicon oxidefilm 2 is formed on a silicon substrate 1. Subsequently, apolycrystalline silicon film 3 doped with phosphor (P) and a siliconnitride film 4 are formed on the silicon oxide film 2 in turn. Next, aphotoresist is formed by a photolithography process into a predeterminedpattern, whereby a mask is formed. The silicon nitride film 4 is etchedby a reactive ion etching (RIE). The polycrystalline silicon film 4 isthen etched with the silicon nitride film 4 serving as a mask so thatthe silicon oxide film 2 is exposed. This state is shown in FIG. 6A.

Subsequently, the silicon oxide film 2 and the silicon substrate 1 areetched so that a trench is formed in the silicon substrate. A siliconoxide film 5 is formed on the inner surface of the trench.Consecutively, a silicon oxide film 6 is deposited in the trench by ahigh density plasma (HDP) process. The silicon oxide film 6 is polishedby a chemical mechanical polish (CMP) process thereby to be planarized.Thereafter, the structure is heated in an atmosphere of nitrogen so asto be formed into the state as shown in FIG. 6B.

In the aforementioned state, wet etching is carried out for the siliconoxide film 6 using a solution of buffered hydrofluoric acid (BHF). Theetching is carried out until a predetermined height or level is achievedon the basis of a surface of the silicon substrate 1. Consequently, anupper surface of the silicon oxide film 6 is located in the middle ofthe polycrystalline silicon film 3. This state is shown in FIG. 6C.Since the foregoing is the wet etching process, the silicon oxide film 5is etched as well as the silicon oxide film 6. Accordingly, part of thepolycrystalline silicon film 3 is exposed as shown in FIG. 6C.

Subsequently, the silicon nitride film 4 is etched by phosphatingthereby to be eliminated. As a result, the structure as shown in FIG. 6Dis obtained. Consecutively, an ONO film 7, a polycrystalline siliconfilm 8 doped with phosphor, a tungsten silicide (WSi) film 9 and asilicon nitride film 10 are sequentially deposited on one another sothat the structure as shown in FIG. 6E is obtained. The ONO film 7 is athree-layer film composed of a silicon oxide film, silicon nitride filmand silicon oxide film.

Thereafter, the silicon nitride film 10 is etched by the RIE process.The WSi film 9, polycrystalline silicon film 8, ONO film 7 andpolycrystalline silicon film 3 are etched by the RIE process with theetched silicon nitride film 10 serving as a mask. A silicon oxide filmis then formed on a side wall of the gate electrode. Thus, a flashmemory is made through the foregoing steps.

For example, JP-A-2002-033476 and JP-A-2002-124563 each disclose atechnique of STI which is an element isolation region formed by burying,with the silicon oxide film, the relatively shallow trench formed in thesilicon substrate.

However, the foregoing conventional techniques have the followingdefects. More specifically, the silicon nitride film 4 serving as astopper film for CMP cannot be polished uniformly when the upper surfaceof the silicon oxide film 6 is flattened. As a result, when the siliconoxide film 6 is etched by the solution of BHF, an amount of etching isdifficult to control, whereupon the height from the surface of thesilicon substrate 1 becomes non-uniform.

The non-uniform height from the surface of the silicon substrate 1results in variations in a coupling ratio of the silicon substrate to agate electrode which will be formed later. This results in an increasein the write time in the characteristic of the device, which increase isundesirable in the practical use.

BRIEF SUMMARY OF THE INVENTION

Therefore, an object of the present invention is to provide a method offabricating a semiconductor device in which control performance in thecontrol of an amount of etching can be improved when etching isperformed for an insulating film buried in a trench formed in thesemiconductor substrate, whereupon a stable device characteristic can beobtained.

The present invention provides a method of fabricating a semiconductordevice comprising sequentially stacking a first insulating film, a firstelectrode film and a silicon nitride film on a first upper surface of asemiconductor substrate, etching the silicon nitride film, the firstelectrode film, the first insulating and the semiconductor substrate toform a trench, burying a second insulating film in the trench,planarizing a second upper surface of the second insulating film usingthe silicon nitride film as a stepper, removing the silicon nitride filmto expose a third upper surface of the first electrode film,isotropically etching the second insulating film so that an upper sidewall of the first electrode film is exposed, a side end portion of afourth upper surface of the second insulating film is located betweenthe first and the third upper surfaces, a middle upper portion of thefourth upper surface of the second insulating film is higher than theside end portion and is lower than the third upper surface relative tothe first upper surface, forming a third insulating film on the thirdupper surface, the upper side wall and the fourth upper surface, andforming a second electrode film on the second insulating film, whereinthe fourth upper surface is entirely covered by the second insulatingfilm.

The invention also provides a method of fabricating a semiconductordevice, comprising sequentially stacking a first insulating film, afirst electrode film and a silicon nitride film on a first upper surfaceof a semiconductor substrate, etching the silicon nitride film, thefirst electrode film, the first insulating film and the semiconductorsubstrate to form a trench, forming a silicon oxide film on a sidesurface of the first electrode film exposed in the trench, burying asecond insulating film in the trench, planarizing a second upper surfaceof the second insulating film using the silicon nitride film as astopper, removing the silicon nitride film to expose a third uppersurface of the first electrode film so that the second upper surfaceprotrudes from the third upper surface, isotropically etching an upperportion of the second insulating film so that an upper side wall of thefirst electrode film is exposed, a side end portion of a fourth uppersurface of the second insulating film is located between the first andthe third upper surfaces, a middle upper portion of the fourth uppersurface of the second insulating film is higher than the side endportion and is lower than the third upper surface relative to the firstupper surface, isotropically etching the second insulating film so thatthe silicon oxide film is exposed, forming a third insulating film onthe third upper surface, the upper side wall, the silicon oxide film andthe fourth upper surface, and forming a second electrode film on thesecond insulating, film, wherein the fourth upper surface is entirelycovered by the second insulating film.

The invention also provides a method of fabricating a semiconductordevice comprising sequentially stacking a first insulating film, apolycrystalline semiconductor film and a semiconductor nitride film on asemiconductor substrate, forming a trench in the semiconductorsubstrate, burying a second insulating film in the trench, therebyforming an element isolation region, selectively removing thesemiconductor nitride film so that the second insulating film buried inthe trench is protruded, and isotropically etching the second insulatingfilm protruded.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome clear upon reviewing the following description of the embodimentwith reference to the accompanying drawings, in which:

FIG. 1 is a schematic plan view of a memory cell of the flash memory inaccordance with a first embodiment of the present invention;

FIGS. 2A and 2B are longitudinal sections taken along line 2A-2A andline 2B-2B respectively;

FIGS. 3A to 3E are longitudinal sections taken across the trench andshowing steps of the fabricating process;

FIGS. 4A to 4E are longitudinal sections taken along the active regionand showing steps of the fabricating process;

FIGS. 5A and 5B are longitudinal sections taken across the trench in thememory cell of the flash memory in accordance with a second embodimentof the invention and showing steps of the fabricating process; and

FIGS. 6A to 6E are longitudinal sections taken across the trench in theprior art and showing steps of the fabricating process.

DETAILED DESCRIPTION OF THE INVENTION

A first embodiment of the present invention will be described withreference to FIGS. 1 to 4E. The invention is applied to a method offabricating a non-volatile memory such as a flash memory in the firstembodiment.

Referring to FIGS. 2A and 2B, a first silicon oxide film 12 (firstinsulating film) serving as a gate oxide film is formed on a surface ofa silicon substrate 11 serving as a semiconductor substrate. The firstsilicon oxide film 12 has a film thickness of 8 nm. A firstpolycrystalline silicon film 13 doped with phosphor is formed on thefirst silicon oxide film 12. The first polycrystalline silicon film 13serves as a floating gate and has a film thickness of 165 nm.

A trench 14 is formed in the silicon substrate 11, the first siliconoxide film 12 and the first polycrystalline silicon film 13 so as tohave a predetermined depth in the silicon substrate. A second siliconoxide film 15 with a film thickness of 6 nm is formed on a bottom andboth sidewalls of the trench 14 so as to extend to a predeterminedlevel. A third silicon oxide film 16 (second insulating film) is buriedin the trench 14 so as to reach a predetermined depth.

The third silicon oxide film 16 has an upper surface formed into twoinclined surfaces 16 a extending from opposite ends of the trench 14 toa central top 16 b thereof respectively. Each inclined surface 16 aincludes a part adjacent to the end of the trench 14 or an upper surfaceend. Each inclined surface 16 a is formed so that the upper surface endthereof is located lower than an upper surface of the firstpolycrystalline silicon film 13 and higher than the upper surface of thesilicon substrate 11. More specifically, each inclined surface 16 a isformed so that the upper surface end is located at a position apredetermined depth D lower than the upper surface of the firstpolycrystalline silicon film 13. Each inclined surface 16 a is formed soas to be downwardly convex or so that an inclination thereof isgradually reduced from the central portion toward the upper surface endthereof.

An oxide-nitride-oxide (ONO) film 17 is formed on upper surfaces of thefirst polycrystalline silicon film 13 and the third silicon oxide film16 buried in the trench 14. The ONO film 17 comprises three films, thatis, a silicon oxide film with a film thickness of 5.5 nm, a siliconnitride film with a film thickness of 8 nm and a silicon oxide film witha film thickness of 5.3 nm. A second polycrystalline silicon film 18added with phosphor is formed on the ONO film 17 so as to bury thetrench 14. The second polycrystalline silicon film 18 has a filmthickness of 80 nm. A tungsten silicide (WSi) film 19 is formed on thesecond polycrystalline silicon film 18 and has a film thickness of 70nm. A second silicon nitride film 20 is formed on the WSi film 19 andhas a film thickness of 300 nm, whereupon a control gate is formed.Further, a fourth silicon oxide film 21 is formed on each sidewall ofthe gate electrode.

An upper surface of the third silicon oxide film 16 buried in the trench14 has a characteristic configuration in the aforementioned structure.This configuration results from employment of the etching process of thepresent invention in the fabrication process as will be described later.One of purposes of the etching process is to improve an forming accuracyin a step of forming the third silicon oxide film 16 so that the endthereof is located at the position lower than the upper surface of thefirst polycrystalline silicon film 13 by the predetermined depth D.

An accurate depth D, when obtained, improves an accuracy in the area ofa portion of the second polycrystalline silicon film 18 opposed to thefirst polycrystalline silicon film 16 with the ONO film 17 formedtherebetween. Consequently, variations in a coupling ratio which isimportant as a device characteristic can be reduced, whereupon a memorycell with a stable characteristic can be obtained.

The fabricating process of the aforesaid memory cell will now bedescribed. The states as shown in FIGS. 3A and 4A are obtained asfollows. Firstly, the silicon substrate 11 is heated in an atmosphere ofmoisture at the temperature of 750° C. so that the first silicon oxidefilm 12 with the film thickness of 8 nm is formed on the surface of thesilicon substrate 11. The first silicon oxide film 12 functions as thegate oxide film. Subsequently, the first polycrystalline silicon film 13with a thickness of 165 nm is deposited on the first silicon oxide film12 by pressure-reduced chemical vapor deposition (RP-CVD). The firstpolycrystalline silicon film 13 is doped with phosphor (H) as impurity.A first silicon nitride film 22 with a film thickness of 70 nm isdeposited on the first polycrystalline silicon film 13.

Subsequently, a photoresist is processed into a predetermined pattern byan ordinary photolithography process. The first silicon nitride film 22is processed by a reactive ion etching (RIE) process with the patternedphotoresist serving as a mask. Consecutively, the films 13, 12 and 11are etched with the first silicon nitride film 22 serving as a mask, sothat the trench 14 is formed in the silicon substrate 11. FIGS. 3A and4A show the sections when the etching has reached the firstpolycrystalline silicon film 13.

Subsequently, the structure is heated in an atmosphere of oxygen at1000° C. so that the second silicon oxide film 15 with a film thicknessof 6 nm is formed on an outer wall of the trench 14. The third siliconoxide film 16 with the film thickness of 700 nm is deposited on thesecond silicon oxide film 15 by a high density plasma (HDP) process,whereupon the structure as shown in FIG. 4B is obtained. The thirdsilicon oxide film 16 is then planarized by a chemical mechanical polish(CMP) process. Thereafter, the structure is thereafter heated in anatmosphere of nitrogen so that the structures as shown in FIGS. 3B and4C are obtained.

The structure is then immersed in a solution of buffered hydrofluoricacid (BHF) in order that the third silicon oxide film on the firstsilicon nitride film 22 may completely be removed. The first siliconnitride film 22 is then removed by the phosphating at 150° C. In thisstate, as shown in FIG. 3C, the upper surface of the third silicon oxidefilm 16 protrudes over the trench 14, whereupon the opposite sides ofthe third silicon oxide film 16 are exposed. Subsequently, as shown inFIGS. 3D and 4D, the structure is immersed in BHF, whereby the thirdsilicon oxide film 16 is etched so that a desired level thereof isobtained relative to the upper surface of the silicon substrate 11. Inthis etching, the protruding third silicon oxide film 16 as shown inFIG. 3 is wet-etched. The etching is caused to progress isotropicallyfrom an exposed portion of the third silicon oxide film 16, whereuponthe etching starts from the upper surface and the exposed sides of thesilicon oxide film 16 and an amount of etching is increased with lapseof time.

Consequently, the etching progresses downward while the arc-shapedinclined face 16 a is being formed which extends from the end toward thecentral upper surface and has a downwardly convex section, as shown inFIG. 3D. In this case, a depth d (see FIG. 3D) from the end of thetrench 14 is obtained by an etching amount proportionate to time. Thus,the inclined faces 16 a extending from the respective ends of the trench14 are joined together in the form of a roof with the centrally formedtop 16 b. Thereafter, the third silicon oxide film 16 is processed byRIE process so as to be etched until the depth D is reached between theopening of the trench 14 and the ends of the upper surface of the thirdsilicon oxide film 16, as shown in FIG. 3E.

Subsequently, as shown in FIG. 4E, the ONO film 17, secondpolycrystalline silicon film 18, and WSi film and second silicon nitridefilm 20 are sequentially deposited on the first polycrystalline siliconfilm 13 by RP-CVD. The ONO film 17 comprises a 5.5-nm-thick siliconoxide film, 8-nm-thick silicon nitride and 5.3-nm-thick silicon oxidefilm. The second polycrystalline silicon film 18 has a film thickness of8 nm. The WSi film 19 has a film thickness of 70 nm. The second siliconnitride film 20 has a film thickness of 300 nm.

Subsequently, a photoresist is patterned into a desired configuration bythe photolithography process. The second silicon nitride film 20 isprocessed by the RIE process with the patterned photoresist serving as amask. The silicon substrate 11 is then exposed to O₂ plasma so that thephotoresist is removed. The WSi film 19, second polycrystalline siliconfilm 18, ONO film 17 and first polycrystalline silicon film 13 are thenprocessed by the RIE process with the second silicon nitride film 20serving as a mask and heated in an atmosphere of oxygen at 1000° C.,whereby the fourth silicon oxide film 21 is formed on the sidewalls ofthe gate electrode. As a result, the structures as shown in FIGS. 2A and2B can be obtained.

According to the foregoing embodiment, when the third silicon oxide film16 buried in the trench 14 is etched, the first silicon nitride film 22is removed so that the third silicon oxide film 16 protrudes.Thereafter, the third silicon oxide film 16 is then immersed in thesolution of BHF. As a result, the third silicon oxide film 16 can beetched isotropically from the surface of the first polycrystallinesilicon film 13. Consequently, an amount of etching in the direction ofdepth of the end can accurately be controlled on the basis of theetching time.

As the result of the above processing, variations in the coupling ratiocan be reduced and accordingly, a stable write can be carried out. Thus,the device characteristic can be rendered stable.

FIGS. 5A and 5B illustrate a second embodiment of the invention. Thesecond embodiment differs from the first embodiment in the fabricatingmethod. More specifically, the process by the RIE process is eliminatedfrom the stage from the state of FIG. 3C to the state of FIG. 3E, andonly the immersion in the solution of BHF is executed so that the thirdsilicon oxide film is etched until the depth D is reached.

When the immersion in the solution of BHF is carried out in the state ofFIG. 5A corresponding to FIG. 3C, the etching progresses isotropicallyand accordingly, the second silicon oxide film 15 formed on thesidewalls is also etched. Since the first embodiment includes theprocess by the RIE process in which anisotropic etching is executed, thesecond silicon oxide film 15 is hard to etch. On the other hand, thesecond silicon oxide film 15 is etched in the wet etching using thesolution of BHF.

The object can be achieved in the case where the second embodiment isemployed when the control of etching amount includes only the control oftime period of etching by the use of BHF. Consequently, the fabricatingprocess can be simplified since the etching by the RIE process iseliminated in the second embodiment.

The invention should not be limited to the foregoing embodiments but maybe modified or expanded as follows. The invention may be applied tosemiconductor devices which exclude flash memories and in which aninsulating film is buried in a trench formed as STI and etching iscarried out.

In the state as shown in FIG. 1, etching is carried out using a solutionof BHF so as to progress isotropically. Subsequently, another etchingprocess may be employed in addition to the RIE process.

The foregoing description and drawings are merely illustrative of theprinciples of the present invention and are not to be construed in alimiting sense. Various changes and modifications will become apparentto those of ordinary skill in the art. All such changes andmodifications are seen to fall within the scope of the invention asdefined by the appended claims.

1. A method of fabricating a semiconductor device comprising:sequentially stacking a first insulating film, a first electrode filmand a silicon nitride film on a first upper surface of a semiconductorsubstrate; etching the silicon nitride film, the first electrode film,the first insulating and the semiconductor substrate to form a trench;burying a second insulating film in the trench; planarizing a secondupper surface of the second insulating film using the silicon nitridefilm as a stopper; removing the silicon nitride film to expose a thirdupper surface of the first electrode film; isotropically etching thesecond insulating film so that an upper side wall of the first electrodefilm is exposed, so that a side end portion of a fourth upper surface ofthe second insulating film is located between the first and the thirdupper surfaces and so that a middle upper portion of the fourth uppersurface of the second insulating film is higher than the side endportion and is lower than the third upper surface relative to the firstupper surface; forming a third insulating film on the third uppersurface, the upper side wall and the fourth upper surface; and forming asecond electrode film on the second insulating film, wherein the fourthupper surface is entirely covered by the second insulating film.
 2. Themethod according to claim 1, wherein the etching step includes a wetetching process.
 3. The method according to claim 2, wherein the wetetching process includes etching with a solution including a bufferedhydrofluoric acid (BHF).
 4. A method of fabricating a semiconductordevice, comprising: sequentially stacking a first insulating film, afirst electrode film and a silicon nitride film on a first upper surfaceof a semiconductor substrate; etching the silicon nitride film, thefirst electrode film, the first insulating film and the semiconductorsubstrate to form a trench; forming a silicon oxide film on a sidesurface of the first electrode film exposed in the trench; burying asecond insulating film in the trench; planarizing a second upper surfaceof the second insulating film using the silicon nitride film as astopper; removing the silicon nitride film to expose a third uppersurface of the first electrode film so that the second upper surfaceprotrudes from the third upper surface; isotropically etching an upperportion of the second insulating film so that an upper side wall of thefirst electrode film is exposed, a side end portion of a fourth uppersurface of the second insulating film is located between the first andthe third upper surfaces, and a middle upper portion of the fourth uppersurface of the second insulating film is higher than the side endportion and is lower than the third upper surface relative to the firstupper surface; anisotropically etching the second insulating film, sothat the silicon oxide film is exposed; forming a third insulating filmon the third upper surface, the upper side wall, the silicon oxide filmand the fourth upper surface; and forming a second electrode film on thesecond insulating film, wherein the fourth upper surface is entirelycovered by the second insulating film.
 5. The method according to claim4, wherein the etching step includes a wet etching process.
 6. Themethod according to claim 5, wherein the wet etching process includesetching with a solution including a buffered hydrofluoric acid (BHF).